The 8051

 
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  The Special Function Registers (SFRs)
   
  The SFRs are in locations 80H to FFH of the on-chip RAM. In the 8051 not all locations are used. These extra locations are used by other family members (8052, etc.) for the extra features these microcontrollers possess.
   
 
7F
 
 
 
General Purpose RAM
 
 
 
30
2F
7F 7E 7D 7C 7B 7A 79 78
2E
77 76 75 74 73 72 71 70
2D
6F 6E 6D 6C 6B 6A 69 68
2C
67 66 65 64 63 62 61 60
2B
5F 5E 5D 5C 5B 5A 59 58
2A
57 56 55 54 53 52 51 50
28
4F 4E 4D 4C 4B 4A 49 48
28
47 46 45 44 43 42 41 40
27
3F 3E 3D 3C 3B 3A 39 38
26
37 36 35 34 33 32 31 30
25
2F 2E 2D 2C 2B 2A 29 28
24
27 26 25 24 23 22 21 20
23
1F 1E 1D 1C 1B 1A 19 18
22
17 16 15 14 13 12 11 10
21
0F 0E 0D 0C 0B 0A 09 08
20
07 06 05 04 03 02 01 00
1F
Register Bank 3
18
17
Register Bank 2
10
0F
Register Bank 1
08
07
Default Register Bank (Bank 0)
00
 
     
F0
F7 F6 F5 F4 F3 F2 F1 F0
B
     
E0
E7 E6 E5 E4 E3 E2 E1 E0
ACC
     
D0
D7 D6 D5 D4 D3 D2 D1 D0
PSW
     
B8
BF BE BD BC BB BA B9 B8
IP
     
B0
B7 B6 B5 B4 B3 B2 B1 B0
P3
     
A8
AF AE AD AC AB AA A9 A8
IE
     
A0
A7 A6 A5 A4 A3 A2 A1 A0
P2
     
99
 
SBUF
98
9F 9E 9D 9C 9B 9A 99 98
SCON
     
90
97 96 95 94 93 92 91 90
P1
     
8D
 
TH1
8C
 
TH0
8B
 
TL1
8A
 
TL0
89
 
TMOD
88
8F 8E 8D 8C 8B 8A 89 88
TCON
87
 
PCON
     
83
 
DPH
82
 
DPL
81
 
SP
80
87 86 85 84 83 82 81 80
P0
RAM
SPECIAL FUNCTION REGISTERS
   
  As you can see, some of the SFRs are bit addressable, including the four ports P0, P1, P2 and P3.
   
  Program Status Word (PSW)
  The PSW is at location D0H and is bit addressable. The table below describes the function of each bit.
   
 
Bit Symbol Address Description
PSW.7 CY D7H Carry flag
PSW.6 AC D6H Auxiliary carry flag
PSW.5 F0 D5H Flag 0
PSW.4 RS1 D4H Register bank select 1
PSW.3 RS0 D3H Register bank select 0
PSW.2 OV D2H Overflow flag
PSW.1 -- D1H Reserved
PSW.0 P D0H Even parity flag
   
   
  Carry Flag
  The carry flag has two functions.
 
  • Firstly, it is used as the carry-out in 8-bit addition/subtraction. For example, if the accumulator contains FDH and we add 3 to the contents of the accumulator (ADD A, #3), the accumulator will then contain zero and the carry flag will be set. It is also set if a subtraction causes a borrow into bit 7. In other words, if a number is subtracted from another number smaller than it, the carry flag will be set. For example, if A contains 3DH and R3 contains 4BH, the instruction SUBB A, R3 will result in the carry bit being set (4BH is greater than 3DH).
  • The carry flag is also used during Boolean operations. For example, we could AND the contents of bit 3DH with the carry flag, the result being placed in the carry flag - ANL C, 3DH
   
  Register Bank Select Bits
  Bits 3 and 4 of the PSW are used for selecting the register bank. Since there are four register banks, two bits are required for selecting a bank, as detailed below.
 
PSW.4 PSW.3 Register Bank Address of Register Bank
0 0 0 00H to 07H
0 1 1 08H to 0FH
1 0 2 10H to 17H
1 1 3 18H to 1FH
   
  For example, if we wished to activate register bank 3 we would use the following instructions -
 
SETB RS1
SETB RS0
   
  If we then moved the contents of R4 to the accumulator (MOV A, R4) we would be moving the data from location 1CH to A.
   
   
  Flag 0
  Flag 0 is a general-purpose flag available to the programmer.
   
   
  Parity Bit
  The parity bit is automatically set or cleared every machine cycle to ensure even parity with the accumulator. The number of 1-bits in the accumulator plus the parity bit is always even. In other words, if the number of 1s in the accumulator is odd then the parity bit is set to make the overall number of bits even. If the number of 1s in the accumulator is even then the parity bit is cleared to make the overall number of bits even.
  For example, if the accumulator holds the number 05H, this is 0000 0101 in binary => the accumulator has an even number of 1s, therefore the parity bit is cleared. If the accumulator holds the number F2H, this is 1111 0010 => the accumulator has an odd number of 1s, therefore the parity bit is set to make the overall number of 1s even.
  As we shall see later in the course, the parity bit is most often used for detecting errors in transmitted data.
   
   
  B Register
  The B register is used together with the accumulator for multiply and divide operations.
 
  • The MUL AB instruction multiplies the values in A and B and stores the low-byte of the result in A and the high-byte in B.
    • For example, if the accumulator contains F5H and the B register contains 02H, the result of MUL AB will be A = EAH and B = 01H.
  • The DIV AB instruction divides A by B leaving the integer result in A and the remainder by B.
    • For example, if the accumulator contains 07H and the B register contains 02H, the result of DIV AB will be A = 03H and B = 01H.
The B register is also bit-addressable.
   
   
  Stack Pointer
  The stack pointer (SP) is an 8-bit register at location 81H. A stack is used for temporarily storing data. It operates on the basis of last in first out (LIFO). Putting data onto the stack is called "pushing onto the stack" while taking data off the stack is called "popping the stack."
  The stack pointer contains the address of the item currently on top of the stack. On power-up or reset the SP is set to 07H. When pushing data onto the stack, the SP is first increased by one and the data is then placed in the location pointed to by the SP. When popping the stack, the data is taken off the stack and the SP is then decreased by one.
  Since reset initialises the SP to 07H, the first item pushed onto the stack is stored at 08H (remember, the SP is incremented first, then the item is placed on the stack). However, if the programmer wishes to use the register banks 1 to 3, which start at address 08H, he/she must move the stack to another part of memory. The general purpose RAM starting at address 30H is a good spot to place the stack. To do so we need to change the contents of the SP.
 
  • MOV SP, #2FH.
  Now, the first item to be pushed onto the stack will be stored at 30H.
   
   
 
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Copyright (c) 2005-2006 James Rogers